Proses 7 nm: Perbedaan antara revisi
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{{Semiconductor manufacturing processes}}
Pada bidang [[Fabrikasi semikonduktor|manufaktur semikonduktor]], dalam Peta Jalan Perangkat dan Sistem Internasional mendefinisikan proses 7
[[TSMC|Taiwan Semiconductor Manufacturing Company]] (TSMC) memulai produksi chip memori [[SRAM]] 256 Mbit menggunakan proses 7
Pada tahun 2017 [[AMD]] merilis prosesor "Roma" (EPYC 2) untuk aplikasi server dan pusat data, yang didasarkan pada proses N7 TSMC <ref name="anandtech">{{cite news |last1=Smith |first1=Ryan |title=AMD "Rome" EPYC CPUs to Be Fabbed By TSMC |url=https://www.anandtech.com/show/13122/amd-rome-epyc-cpus-to-be-fabbed-by-tsmc |access-date=18 June 2019 |work=[[AnandTech]] |date=July 26, 2018}}</ref> dengan fitur 64 inti dan 128 utas. Mereka juga merilis prosesor desktop konsumen "Matisse" dengan fitur 16 inti dan 32 utas. Namun, cetakan I/O pada modul multi-chip Roma (MCM) dibuat dengan proses 14
{| class="wikitable" style="text-align:center"
|+ Proses node 7 nm dan proses offering
!
! colspan=2|[[Samsung Electronics|Samsung]]
! colspan=4|[[TSMC]]
! [[Intel]]
! colspan=3|[[Semiconductor Manufacturing International Corporation|SMIC]]
|-
! Process name
| 7LPP<ref>{{Cite web |title=VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM |url=https://fuse.wikichip.org/news/1479/vlsi-2018-samsungs-2nd-gen-7nm-euv-goes-hvm/ |website=WikiChip |date=August 4, 2018 |access-date=September 16, 2022}}</ref><ref>{{Cite web |title=Samsung Electronics Starts Production of EUV-based 7nm LPP Process |url=https://news.samsung.com/global/samsung-electronics-starts-production-of-euv-based-7nm-lpp-process |website=Samsung Newsroom |date=October 18, 2018 |access-date=September 16, 2022}}</ref>
| 6LPP<ref>{{cite web | url=https://www.anandtech.com/show/15538/samsung-starts-mass-production-at-v1-a-dedicated-euv-fab-for-7nm-6nm-5nm-4nm-3nm-nodes | title=Samsung Starts Mass Production at V1: A Dedicated EUV Fab for 7nm, 6nm, 5nm, 4nm, 3nm Nodes }}</ref>
| N7<ref>IEDM 2016</ref>
| N7P<small></small><ref name=n7p>{{Cite web |last=Schor |first=David |date=July 28, 2019 |title=TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging|url=https://fuse.wikichip.org/news/2567/tsmc-talks-7nm-5nm-yield-and-next-gen-5g-and-hpc-packaging/ |website=WikiChip Fuse |language=en-US |access-date=September 13, 2019}}</ref>
| N7+<ref>{{Cite web|url=https://www.eetimes.com/tsmc-goes-photon-to-cloud/|title=TSMC Goes Photon to Cloud|date=October 4, 2018|website=EETimes}}</ref>
| N6
| Intel 7<ref name=":3" />{{disputed inline|Intel 7|date=September 2023}} (10nm)<ref>{{cite news |last1=Bonshor |first1=Gavin |title=Intel Core i9-13900K and i5-13600K Review: Raptor Lake Brings More Bite |url=https://www.anandtech.com/print/17601/intel-core-i9-13900k-and-i5-13600k-review |access-date=28 September 2023 |work=[[AnandTech]] |date=20 October 2022}}</ref>
| N+1 (>7 nm)
| N+2 (7 nm)
| 7 nm EUV
|-
! style="text-align:left;" | Transistor density (MTr/mm<sup>2</sup>)
| 95.08–100.59<ref>{{cite web | url=https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/ | title=Can TSMC Maintain Their Process Technology Lead | date=July 18, 2023 }}</ref><ref>{{cite web | url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/ | title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements | date=July 5, 2022 }}</ref>
| {{unknown}}
| colspan=2|91.2–96.5<ref name="Jones">{{cite web |last1=Jones |first1=Scotten |title=TSMC and Samsung 5nm Comparison |url=https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/8157-tsmc-and-samsung-5nm-comparison/ |website=Semiwiki |date=May 3, 2019 |access-date=30 July 2019}}</ref><ref>{{cite web | url=https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/ | title=N3E Replaces N3; Comes in Many Flavors | date=September 4, 2022 }}</ref>
| 113.9<ref name="Jones" />
| 114.2<ref name=":0">{{Cite web |last1=Schor |first1=David |date=April 16, 2019 |title=TSMC Announces 6-Nanometer Process |url=https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/ |website=WikiChip Fuse |language=en-US |access-date=May 31, 2019}}</ref>
| 100.76–106.1<ref>{{citation| url =https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/| title = Can TSMC Maintain Their Process Technology Lead | first = Scotten|last = Jones | date = July 18, 2023 }}</ref><ref>{{cite web | url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros | title=Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?! }}</ref> 60.41<ref>{{cite web
|first=David
|last=Schor
|url=https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/
|title=A Look At Intel 4 Process Technology
|website=WikiChip Fuse
|date=2022-06-19
}}</ref>
| 89<ref>{{citation| url =https://news.yahoo.com/smic-mass-produces-14nm-nodes-003531507.html| title = SMIC Mass Produces 14nm Nodes, Advances To 5nm, 7nm | date = September 16, 2022 }}</ref>
| {{unknown}}<ref>{{Cite web |title=百度安全验证 |url=https://wappass.baidu.com/static/captcha/tuxing.html?ak=572be823e2f50ea759a616c060d6b9f1&backurl=https%3A%2F%2Fmbd.baidu.com%2Fnewspage%2Fdata%2Flandingsuper%3Fid%3D1776250041672964514%26third%3Dbaijiahao%26baijiahao_id%3D1776250041672964514%26wfr%3D%26c_source%3Dkunlun%26c_score%3D0.999100×tamp=1694030583&signature=98639f61033724d3dda06d0cfa835744 |access-date=2023-09-06 |website=wappass.baidu.com}}</ref>{{Citation needed|reason=the source (百度安全验证) is just a blogger not a reliable media|date=January 2025}}
| {{unknown}}
|-
! style="text-align:left;" | SRAM bit-cell size
| 0.0262 μm<sup>2</sup><ref name=":1" />
| {{unknown}}
| colspan=2|0.027 μm<sup>2</sup><ref name=":1">{{Cite web|url=https://fuse.wikichip.org/news/1479/vlsi-2018-samsungs-2nd-gen-7nm-euv-goes-hvm/|title=VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM|date=2018-08-04|website=WikiChip Fuse|language=en-US|access-date=2019-05-31}}</ref>
| {{unknown}}
| {{unknown}}
| 0.0312 μm<sup>2</sup>
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Transistor gate pitch
| 54 nm
| {{unknown}}
| colspan=4|57 nm
| 54 nm
| {{unknown}}
| 63 nm
| {{unknown}}
|-
! style="text-align:left;" | Transistor fin pitch
| 27 nm
| {{unknown}}
| colspan=2| N/A
| {{unknown}}
| {{unknown}}
| 34 nm
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Transistor fin height
| {{unknown}}
| {{unknown}}
| colspan=2| N/A
| {{unknown}}
| {{unknown}}
| 53 nm
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Minimum (metal) pitch
| 46 nm
| {{unknown}}
| colspan=4|40 nm
| 40 nm<ref>{{cite web |last1=Smith |first1=Ryan |date=June 13, 2022 |title=Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance |url=https://www.anandtech.com/show/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance |website=AnandTech |access-date=September 17, 2022}}</ref>
| {{unknown}}
| 42 nm
| {{unknown}}
|-
! style="text-align:left;" | EUV implementation
| 36 nm pitch metal;<ref name="7nml" /><br />20% of total layer set
| {{unknown}}
| colspan=2|None, used self-aligned quad patterning ([[Multiple patterning|SAQP]]) instead
| 4 layers
| 5 layers
| None. Relied on [[Multiple patterning|SAQP]] heavily
| None
| None
| Yes (after N+2)
|-
! style="text-align:left;" | EUV-limited wafer output
| 1500 wafers/day<ref name=s7nm>{{Cite web|url=https://www.eetimes.com/samsung-ramps-7nm-euv-chips/|title=Samsung Ramps 7nm EUV Chips|date=October 17, 2018|website=EETimes}}</ref>
| {{unknown}}
| colspan=2|N/A
| ~ 1000 wafers/day<ref>{{Cite web|url=http://www.tsmc.com/uploadfile/ir/quarterly/2018/1yZjH/E/TSMC%201Q18%20transcript.pdf|title=TSMC Q1 2018 earnings call transcript, p.12|access-date=October 14, 2018|archive-date=October 14, 2018|archive-url=https://web.archive.org/web/20181014091359/http://www.tsmc.com/uploadfile/ir/quarterly/2018/1yZjH/E/TSMC%201Q18%20transcript.pdf}}</ref>
| {{unknown}}
| N/A
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Multipatterning <br />(≥ 2 masks on a layer)
| Fins<br />Gate<br />Vias (double-patterned)<ref name="vlsi">W. C. Jeong et al., VLSI Technology 2017.</ref><br />Metal 1 (triple-patterned)<ref name="vlsi" /><br />44 nm pitch metal (quad-patterned)<ref name="7nml" />
| {{unknown}}
| colspan=2|Fins<br />Gate<br />Contacts/vias (quad-patterned)<ref>{{Cite web |last1=Dillinger |first1=Tom |date=March 23, 2017 |title=Top 10 Updates from the TSMC Technology Symposium, Part II |url=https://semiwiki.com/semiconductor-manufacturers/tsmc/6676-top-10-updates-from-the-tsmc-technology-symposium-part-ii/ |website=SemiWiki |access-date=September 16, 2022}}</ref><br />Lowest 10 metal layers
| Same as N7, with reduction on 4 EUV layers
| Same as N7, with reduction on 5 EUV layers
|
| multipatterning with DUV
| multipatterning with DUV
| {{unknown}}
|-
! style="text-align:left;" | Release status
| {{success|2018 risk production}}<br />2019 production
| {{success|2020 production}}
| {{success|2017 risk production}}<br />2018 production<ref name="tsmc"/>
| {{success|2019 production}}
| {{success|2018 risk production<ref name="tsmc"/><br />2019 production}}
| {{success|2020 risk production}}<br />2020 production
| {{success|2021 production}}<ref name=":3">{{Cite web|last=Cutress|first=Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=2021-07-27|website=www.anandtech.com}}</ref>
| {{success|April 2021 risk production, mass production unknown}}
| {{success|Late 2021 risk production, quietly produced since July 2021}}<ref>{{Cite web |author=Paul Alcorn |date=21 July 2022 |title=China's SMIC Shipping 7nm Chips, Reportedly Copied TSMC's Tech|url=https://www.tomshardware.com/news/china-chipmaker-smics-7nm-process-is-reportedly-copied-from-tsmc-tech|website=Tom's Hardware}}</ref>
| {{no|Postponed due to US embargo}}
|-
|}
== Lihat pula ==
* [[International Technology Roadmap for Semiconductors]]
* [[Fabrikasi semikonduktor]]
* [[Fotolitografi]]
* [[Litografi ultraviolet ekstrim]]
* [[Litografi rendam]]
* [[ASML Holding]] pemasok sistem [[fotolitografi]] terbesar, terutama untuk industri [[semikonduktor]].
* [[Semiconductor Equipment and Materials International|SEMI]] — The semiconductor industry trade association
* [[Electronic design automation]]
* [[Fab (semiconductors)|Fab]]
* [[Foundry]]
* [[GDS-II]]
* [[OASIS (standard)|OASIS]]
* [[Taiwan Semiconductor Manufacturing Company]] TSMC
* [[Applied Materials]]
* [[KLA Corporation]]
* [[Lam Research]]
* [[Tokyo Electron]]
* [[GlobalFoundries]]
* [[United Microelectronics Corporation]]
* [[Semiconductor Manufacturing International Corporation]]
* [[Shanghai Micro Electronics Equipment]]
* [[Sirkuit terpadu]]
* [[Mikroprosesor]]
* [[Unit Pemroses Sentral]]
* [[MOSFET]]
* [[Transistor]]
* [[Semikonduktor]]
* [[Nanometer]]
==Referensi==
{{Reflist}}
==
* [https://en.wikichip.org/wiki/7_nm_lithography_process 7 nm lithography process]
Baris 17 ⟶ 183:
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