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Each [[bit]] in an SRAM is stored on four [[transistor]]s that form two cross-coupled [[logical_not|inverter]]s. This storage cell has two stable states which are used to denote '''0''' and '''1'''. Two additional ''access'' transistors serve to control the access to a storage cell during read and write operations. It thus typically takes six [[MOSFET]]s to store one memory bit.
The symmetric circuit structure allows the value of a memory location to be read much faster than in a [[Dynamic Random Access Memory|DRAM]].
Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. As opposed to this, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.
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Another current role for SRAM is that it is significantly easier to work with at the hobbyist level than [[DRAM]]. There is no need to deal with the refresh cycles of DRAM, and the address and signal pins are separate rather than multiplexed. Therefore the chip has a very straightforward pin-out: power, ground, some address pins, some data pins, and three control pins "write enable", "chip enable" and "output enable". "Chip enable" is for use in systems containing multiple SRAM chips; a [[demultiplexer]], such as a 74LS154, converts some upper bits of the address into a chip-enable for one of sixteen chips.
To write to the chip, the address is presented on the address pins and the desired data on the data pins, then the appropriate chip-enable is set, and then the write-enable. To read from it, the controller first presents the address, then the chip-enable, then the output-enable.
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